1. Field of the Invention
The present invention relates generally to a Neuro device, and more particularly, to an improvement of a variable resistor playing a weighting role in a Neuro device.
2. Description of the Prior Art
A Neuro device is a representation of a nerve cell constituting human brains, eyes and the like, that is, a neuron by an electronic circuit.
FIG. 18 is a diagram schematically showing the construction of a neuron. Referring to FIG. 18, a neuron comprises a plurality of synapses and dendrites 1, one nerve cell 2, and one axon. The synapse and dendrite 1 corresponds to an input-output interface and an input line in an electronic circuit. The nerve cell 2 corresponds to an operational amplifier in the electronic circuit. The axon 3 corresponds to an output line in the electronic circuit. This neuron acts as follows. Signals V1, V2 and V3 are respectively applied to the three synapses and dendrites 1. Consequently, in the synapses and dendrites 1, weights W1, W2 and W3 are respectively added to the signals V1, V2 and V3. Accordingly, the signals entering the nerve cell 2 are weighted, to be V1.W1, V2.W2 and V3.W3. The weighted three signals are added in the nerve cell 2, to be .alpha.=V1.W1, V2.W2 and V3.W3. If .alpha. exceeds a predetermined value, a signal V4 having a value inherent to this neuron is outputted to the succeeding nerve cell.
The Neuro device is a representation of this neuron by the electronic circuit. In the electronic circuit, the synapse, the nerve cell, and the axon and the dendrite constituting the neuron are generally formed of a resistor, an arithmetic circuit, and wires, respectively.
FIGS. 19, 20 and 21 show examples of circuits of conventional Neuro devices.
The circuit shown in FIG. 19 comprises n (n : a natural number) input terminals 4, resistors R1, R2, ..., Rn respectively connected to the input terminals 4, an arithmetic circuit 100 to which signals from the resistors R1, R2, ..., Rn are together applied, and an output terminal 5 to which a signal from the arithmetic circuit 100 is outputted. When input voltages V1, V2, ..., Vn are respectively applied to the input terminals 4, currents flowing into the arithmetic circuit 100 through the resistors R1, R2, ..., Rn are respectively V1/R1, V2/R2, ..., Vn/Rn. That is, the input signals are respectively weighted by the resistors R1, R2, ..., Rn. In the arithmetic circuit 100, the input currents are added. If the total of the input currents is not less than a predetermined reference current, an output voltage Vx is outputted to the output terminal 5. This voltage Vx is applied to the succeeding Neuro device which is not shown.
In the circuit shown in FIG. 19, the resistance value of each of the resistors R1 to Rn is a fixed value, so that the weighting cannot be changed. Consequently, a pattern for weighting the input signal is fixed. Therefore, it is proposed that resistors R1, R2, ..., Rn connected to the respective input terminals 4 are made variable, as in an equivalent circuit of FIG. 20.
FIG. 21 shows an example of a circuit of a Neuro device in which resistors for weighting input signals are variable resistors. Referring to FIG. 21, reference numerals 6 denote weighting portions. The weighting portions 6 respectively output voltages corresponding to predetermined weights W1, W2, ..., Wn. Each of the voltages is applied to a gate of a MOSFET (Field Effect Transistor of Metal-Oxide Semiconductor) 7. The ON-state resistance value of the MOSFET 7 varies depending on the voltage applied to the gate thereof. Accordingly, a variable resistor for varying the ON-state resistance value of the MOSFET 7 by changing the voltage outputted from the weighting portion 6 is constructed. In the variable resistor of such construction, the weighting portion 6 has been conventionally constituted by a cell, a capacitor or a floating gate in a static RAM (see NIKKEI MICRODEVICES, December, 1990, pp. 42 to 51).
In the conventional circuit arrangement as shown in FIG. 21, however, it is difficult to obtain a reliable Neuro device. The reason for this is that the ON-state resistance value of the MOSFET 7 greatly varies depending on the very small change in the voltage applied to the gate thereof.
Furthermore, the conventional technique in which the weighting portion 6 is constituted by the cell or the capacitor in the static RAM has the disadvantages in that the area of the variable resistor is large, and data cannot be held in a state where a power supply voltage is off because the cell and the capacitor are volatile. On the other hand, the conventional technique in which the weighting portion 6 is constituted by the floating gate has the disadvantage in that it is difficult to implant a desirable amount of charge into the floating gate.